The EPI (Epitaxy) process is a key material growth technology in semiconductor manufacturing. It epitaxies a layer of high-quality single-crystal silicon or silicon alloy material on a single-crystal silicon substrate to provide a better material platform for subsequent device manufacturing. It is widely used in power devices, CMOS, high-speed devices, BiCMOS, RF chips, etc.
1. Definition of EPI process
Epitaxy (Epitaxial growth) refers to the growth of the same or different materials along the lattice direction on a crystal substrate (usually single-crystal silicon) with an existing lattice structure to form a new single-crystal material layer with the same crystal orientation as the substrate.
2. The main purpose of the EPI process
| Purpose | Illustrate |
| Improved crystal quality | Providing high-quality, low-defect density growth layers |
| Controlling doping concentration and type | A region that is lower (low doped) or more doped than the substrate, forming a drift region. |
| Introducing Strain Engineering | Introducing SiGe or stressors in the EPI layer to improve carrier mobility (such as Strained Silicon) |
| Provides device isolation layer | Supports the formation of vertical isolation layers in SOI, BiCMOS and other structures |
| Supports high voltage device structures |
For example, LDMOS and IGBT require a thick, low-doped EPI layer as a drift region to increase the breakdown voltage.
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3. EPI process classification
1. Classification by material type
| Type | Describe |
| Si EPI | Most common, single crystal silicon epitaxial layer |
| SiGe EPI | Germanium-doped silicon epitaxial layers for strain engineering or RF devices |
| Si:C EPI | Carbon-doped silicon epitaxial layer to limit boron diffusion (PMOS) |
| III-V EPI | GaAs, InP, etc., mainly used in optoelectronic devices, high-speed devices (usually not in the CMOS main line) |
2. Classification by doping type
| Type | Describe |
| N-type EPI | Phosphorus/Arsenic doped, suitable for drift layer of power devices such as N-LDMOS |
| P-type EPI | Boron doped, suitable for P-type CMOS device structure |
| Intrinsic EPI | Very low doping, close to intrinsic silicon, for high voltage applications |
3. Classification by structural form
| Type | Illustrate |
| Single-layer EPI | Single thickness/doping structure |
| Multilayer EPI | Graded doping, such as alternating P/N layers required for superjunction SJ MOSFET structures |
| Selective EPI | Grow only in local areas of the wafer (such as source/drain), used for FinFET or strained structures |
4. Overview of EPI process flow
Substrate preparation:
- Polished silicon wafer cleaning (RCA cleaning);
- Remove the original oxide layer (HF or HCl gas treatment);
- Surface reduction to clean Si (100) bare surface
Crystal growth (epitaxial reaction):
-Use CVD (Chemical Vapor Deposition) process;
-Common reaction gases:
-SiH₄ (silane), SiCl₄, HCl
-Doping gas: PH₃ (phosphorus), B₂H₆ (boron), AsH₃ (arsenic)
Process control parameters:
-Temperature: 900°C~1200°C (hot wall or cold wall reactor)
-Pressure: low pressure or atmospheric pressure;
-Growth rate: <1μm/min (strict requirements on thickness/uniformity)
Post-processing:
-Test thickness uniformity, doping distribution;
-Step height measurement;
-Surface defect analysis (e.g. using optics/SEM/AFM/ETC to detect crystal dislocation)
5. Common EPI application scenarios
1. Power devices (LDMOS, IGBT, Diode)
Low doping, thick EPI layer forms a drift region;
Increase breakdown voltage and reduce conduction loss.
2. FinFET/CMOS high-performance devices
Selective SiGe EPI in source/drain;
Introducing strain, improving mobility and reducing resistance.
3. RF devices (RF CMOS, HBT)
Precisely controlled SiGe EPI layer forms heterogeneous structures (such as SiGe HBT);
Provides better frequency response and low noise characteristics.
6. Challenges of EPI Process
| Challenge | Illustrate |
| Lattice defect control | The EPI layer must maintain a low dislocation density (e.g. TDD < 1e4) |
| Doping precision control | To achieve < 5% variation, especially in multi-layer structures |
| Interface cleanliness | Interface impurities/oxidation can cause crystal mismatch and electrical degradation |
| Step height/stair control | High requirements for subsequent photolithography and flatness |
| Cost | EPI equipment is expensive, slow and costly |
7. Relationship between EPI and other technologies
| Technology | Relation |
| SOI | EPI can be grown on silicon layers for device fabrication |
| FinFET | Source/Drain often uses Selective EPI to introduce strain |
| Super Junction | Multiple layers of alternating P/N type EPI layers form a high voltage MOS structure |
| High Voltage CMOS | The EPI layer constitutes a high-voltage drift region and jointly optimizes Ron and BV with the Buried Layer |
Summarize
| Project | Content |
| Purpose | Providing high-quality, doping-controlled single crystal structures |
| Way | Chemical vapor deposition (CVD) single crystal epitaxy on wafers |
| Application | High voltage devices, RF, FinFET, SOI, power devices, etc. |
| Challenge | Crystal defects, doping accuracy, surface flatness, cost |
