1. Background: Why isn't silicon wafers enough?
The first step in semiconductor manufacturing is obtaining a polished single-crystal silicon wafer (usually a Czochralski wafer grown using the CZ method).
However, although these wafers are single crystals, their surfaces may not meet the stringent device requirements for purity, defect density, doping accuracy, and structure.
Particularly in advanced process nodes and high-performance devices, creating active regions directly on the original wafer presents limitations:
- The high oxygen content in the wafer bulk (CZ silicon often has oxygen precipitates), which affects device minority carrier lifetime and leakage.
- The wafer doping profile cannot be precisely adjusted (especially when ultra-shallow junctions or gradient structures are required).
- Micro-defects such as dislocations and scratches may exist on the surface, directly affecting yield.
- Some devices require heterogeneous materials (such as SiGe, GaAs-on-Si, and SiC-on-Si)-materials that cannot be achieved with the wafer itself.
This necessitates a controllable "resurfacing" technology-the epitaxial growth (EPI) process.
2. Core Definition of the EPI Process
Epitaxy refers to the growth of a single-crystal thin film on a single-crystal substrate with the same crystal orientation as the substrate.
This can be either homoepitaxial (Si on Si) or heteroepitaxial (SiGe on Si, GaN on SiC, etc.).
Key Features:
The epitaxial layer "inherits" the substrate's lattice structure (crystal orientation and alignment) and has a low defect density.
Thickness is controllable (from a few nanometers to tens of microns).
Doping type, concentration, and gradient can be precisely adjusted according to the design.
3. Why use the EPI process?
This can be explained from three perspectives: performance, process, and the introduction of new materials:
3.1 Performance Improvement
Reducing Defect Density
EPI can grow a "defect-free layer" that isolates substrate defects from the active region, thereby increasing minority carrier lifetime (particularly important for power devices). Optimizing Doping Structures
Ultra-shallow junctions or graded doping profiles can be achieved, improving breakdown voltage and conduction characteristics.
Improving Electrical Performance
High-resistance epitaxial layer (EPI) layers can reduce parasitic capacitance (suitable for high-frequency devices), while thick epitaxial layers can improve the withstand voltage of power devices.
3.2 Process Controllability
Device Isolation
Using a high-resistance EPI layer can improve isolation between devices and reduce parasitic crosstalk.
Reducing Latch-Up
In CMOS, the epitaxial layer can suppress the triggering of parasitic thyristor structures.
Flexible Thickness
Different products can have customized EPI thicknesses on the same substrate (especially common in power, analog, and RF applications).
3.3 Introduction of New Materials
Strain Engineering
SiGe epitaxy, SiC epitaxy, and GaN epitaxy are all achieved through EPI.
Heterogeneous Integration
In silicon photonics, MEMS, and power devices, EPI can be used to grow III-V materials on silicon. Superlattice structures such as HBTs and quantum well lasers require alternating deposition of layers of materials with different band gaps, necessitating EPI.
4. Common EPI Process Types
| Process | Features | Applications |
|---|---|---|
|
Si EPI(homogeneous coverage) |
High-purity Si layers grown on Si substrates |
CMOS,power devices |
|
SiGe EPI |
Controllable Ge content, strain-coated |
PMOS acceleration,SiGe HBT |
|
SiC EPI |
High hardness, high thermal conductivity, high breakdown field | Power electronics (silicon carbide MOSFET) |
|
GaN EPI |
Wide bandgap, high electron mobility | High-frequency, high-power RF |
|
Ge EPI on Si |
Optoelectronic integration, strained CMOS | Silicon photonics, infrared detection |
5. Technical Challenges of the EPI Process
Interface Defects: The lattice matching between the epitaxial layer and the substrate requires extremely high precision, otherwise dislocations will be generated.
Stress Management: Excessive stress during heteroepitaxial growth can cause warping or cracking.
Precise Doping Control: The concentration range can reach 10¹³–10²⁰ cm⁻³, with an accuracy requirement of ±1%.
Thickness Uniformity: Large-diameter (300mm) wafers require thickness uniformity of <1%.
6. Summary
The EPI process emerged because it can "reshape" the wafer to create a high-quality, designable, low-defect, and controllable doping surface layer. This not only extends the lifespan of silicon CMOS, but also provides a path for the implementation of new materials and novel device structures.
Without EPI, it would be difficult to achieve today's high-performance PMOS, power MOSFET, SiGe HBT, and SiC/GaN power devices.
