What Is The Difference Between Silicon Wafer <100>, <110>, <111>?

1. Crystal structure and atomic arrangement
1.1 Atomic arrangement

<100> Crystal direction

• Surface atomic arrangement: atoms are arranged along the edge of the cube to form a square grid.
• Atomic density: the lowest (about atoms/cm²), the atomic distance is large, and the surface energy is high.
• Bonding direction: the surface atomic bonds are perpendicular to the crystal plane and have high chemical activity.

100                                              010                                              001

<110> Crystal surface

• Atomic arrangement: Arranged along the diagonal direction of the cube face to form a rectangular grid.
• Atomic density: Medium (about atoms/cm²).
• Bonding direction: The surface atomic bonds are tilted at 45°, with high mechanical strength.

1.2 Surface energy and chemical stability
<111> > <110> > <100> (Ranking of chemical stability)

• <111> The surface has the best corrosion resistance due to its high atomic density and strong bonding;
• <100> The surface atoms are loose and easily etched by chemicals (such as KOH).

2. Anisotropic behavior
2.1 Wet chemical etching (taking KOH as an example)

• Key Mechanism: The etching rate of KOH on silicon is directly related to the degree of exposure of atomic bonds along the crystal direction.
• <100>: Atomic bonds are easily attacked by OH⁻, and the etching rate is fast;
• <111>: Atomic bonds are tightly shielded and almost unreactive.

2.2 Dry etching (such as plasma etching)

• The crystal orientation has little effect, but the <111> high-density surface may cause micro-masking effect and form local roughness.

3. Comparison of process characteristics
3.1 Oxide layer quality

• <100> Advantages: Low-defect oxide layer is a core requirement of CMOS devices.

3.2 Carrier mobility (300K)

• Reason: The <100> crystal plane matches the symmetry of the silicon lattice, reducing carrier scattering.

4. Mechanical and thermal properties
4.1 Mechanical strength <111> > <110> > <100>

• The fracture toughness is: 0.8 MPa·m¹/², 0.7 MPa·m¹/², 0.6 MPa·m¹/²
• Application example: MEMS pressure sensors mostly use <110> wafers because their fatigue resistance is better than <100>.

4.2 Thermal expansion coefficient
The anisotropy of silicon leads to differences in thermal expansion coefficients in different crystal directions:

• <100>: 2.6×10⁻⁶ /K
• <110>: 1.6×10⁻⁶ /K
• <111>: 0.5×10⁻⁶ /K

Impact: <111> wafers are prone to stress in high-temperature processes, and thermal budgets need to be carefully designed.

5. Application scenarios
5.1 <100> crystal orientation

• Integrated circuits (ICs): More than 95% of the world's logic chips (such as CPUs and DRAMs) use <100> wafers.
• Advantages: low interface state density, high carrier mobility, and oxide layer uniformity.
• Solar cells: Pyramid structure formed by anisotropic etching, with a reflectivity of <5%.
• Example: TSMC's 3nm process is based on <100> silicon, with a gate length of 12nm.

5.2 <110> Crystal Orientation
MEMS devices:

• Accelerometers: Use vertical deep grooves to make movable masses (aspect ratio >20:1).
• Pressure sensors: The piezoresistance coefficient is the largest in the <110> direction (e.g., the π₁₁ coefficient of silicon is 6.6×10^-11  Pa⁻¹).
• High-frequency devices: <110> silicon substrates can reduce lattice mismatch stress in GaAs epitaxial growth.

5.3 <111> Crystal Orientation
Optoelectronic devices:

• GaN epitaxial: High lattice match with <111> silicon (17% mismatch, compared to <100> 23%).
• Quantum dot arrays: High-density atomic planes provide ordered nucleation sites.
• Nanostructure templates: Used for AFM probe tips or nanowire growth.

6. Cost and industrial chain

Cost drivers:

• <100> Wafers have the lowest cost due to economies of scale;
• <111> Wafers require special cutting and polishing processes.

Summary: The key basis for selecting crystal orientation