Reading A Silicon Wafer's “Health Report”: How To Understand The Key Parameters

For many buyers and process engineers, the wafer specification sheet is a document "read once at contract signing, and never opened again." Yet silicon wafers are a highly parameter-standardized industry: international standards such as SEMI M1 define dimensions, flatness and electrical parameters in a universal language. Spec sheets from Supplier A and Supplier B look nearly identical - the differences hide in the numbers and in consistency.

One sentence captures where wafer parameters come from: crystal growth defines the "constitution"; shaping defines the "physique"; the COA simply reads the results back to you.

 

 

The following sections cover the three major families: geometry, oxygen and resistivity.

 

2.1 Thickness

Wafer thickness increases with diameter. Typical mainstream values:

Diameter	Typical Thickness (example)
6 inch (150 mm)	675 ± 20 µm
8 inch (200 mm)	725 ± 20 µm
12 inch (300 mm)	775 ± 20 µm

Thickness defines the process window for backside thinning (advanced-node wafers are thinned to tens of microns), chip heat dissipation and mechanical strength. The tighter the tolerance, the more margin for thinning and probe testing.

 

2.2 TTV: Thickness Consistency

TTV (Total Thickness Variation) is the difference between the maximum and minimum thickness measured on a single wafer - a measure of how evenly thick the wafer is. It is a fundamental parameter for vacuum chucking, lithography focus and bonding: if one side of the wafer is thicker than the other, the surface deforms when chucked.

 

2.3 TIR and Site Flatness: Lithography's Hidden Threshold

TIR (Total Indicated Reading) measures the overall deviation of the front surface relative to a reference plane. What actually bottlenecks advanced processes, however, is site flatness (SFQR/LTV) - lithography scanners focus field by field,

so even if the wafer is globally flat, a gentle local slope will still defocus the exposure. The more advanced the node, the smaller the depth of focus (DOF) and the stricter the site-flatness requirement: at leading nodes SFQR has entered the 0.1–

0.2 µm range.

 

2.4 Bow and Warp: Deformation of the Median Surface

Bow describes the deviation of the center point of the wafer's median surface from a reference plane; Warp describes the maximum deviation of that median surface. Both reflect residual stress left by slicing and heat treatment. Wafers with excessive warp tend to jam in robotic handling, crack during thinning and suffer direct hits to bonding yield.

 

Typical ranges at a glance (example values; always refer to the vendor's spec sheet):

Parameter	Typical Range	Main Process Impact
Thickness	See table above	Thinning window, heat dissipation, mechanical strength
TTV	Prime grade ≤ 1–2 µm	Chucking, litho focus, bonding
TIR / SFQR	Site level 0.1–0.2 µm (advanced nodes)	Depth of focus, overlay accuracy
Bow / Warp	Typically ≤ 20–30 µm; stricter for Prime grade	Handling, thinning, bonding

 

3.1 Where the Oxygen Comes From

In Czochralski (CZ) growth, molten silicon is in direct contact with the quartz crucible (SiO₂), so oxygen inevitably dissolves into the melt and enters the crystal. CZ wafers therefore always contain oxygen, with typical interstitial oxygen concentrations of 10–16 ppma (new ASTM scale). The only route to "nearly oxygen-free" silicon is the float-zone (FZ) method - at the cost of diameter limits and higher expense.

 

3.2 Oxygen Is a Double-Edged Sword

The upside: At appropriate concentrations, oxygen forms oxygen precipitates during subsequent heat treatment that getter metallic contamination from the bulk - this is internal gettering (IG), effectively a "built-in vacuum cleaner" for the device active region. Oxygen also strengthens the wafer mechanically and suppresses slip during high-temperature processing.

The downside: Around 450 °C oxygen forms thermal donors, interfering with resistivity measurements and device- parameter stability; excessive or oversized oxygen precipitates generate dislocations and stacking faults that, in severe cases, punch through into the device region. For large 12-inch crystals the thermal field is harder to control, and radial oxygen uniformity is one of the core challenges of crystal growth.

 

4.1 What and How Much Is Doped

• P-type wafers are doped with boron (B); N-type with phosphorus (P), antimony or arsenic.
• Lightly doped: typically 1–100 Ω·cm - the mainstream substrate for logic, memory and analog chips.
• Heavily doped: typically 0.001–0.02 Ω·cm - used as power-device substrates or buried layers.
• High-resistivity: ≥ 1 kΩ·cm, achieved with FZ or MCZ - serving RF-SOI, image sensors and power-module applications.

 

4.2 How It Is Measured and What to Watch

Resistivity is measured by the four-point probe method (SEMI MF84) or contactless methods. Beyond the absolute value, the radial resistivity gradient (typically required ≤ 5%) is equally critical - if substrate resistivity is non-uniform, breakdown voltage and threshold voltage will vary "from wafer to wafer" in the finished devices.