Backside Seal Technology For 200 mm Epitaxial Substrates: Poly-Si, LTO, And Autodoping Control

When a heavily doped substrate enters an epitaxial reactor, the intended result is a lightly doped epitaxial layer with controlled resistivity. Yet the resistivity near the wafer edge may deviate from target. In other cases, a substrate meets all incoming geometric specifications but develops particles or abnormal warpage after epitaxy and cleaning. The cause may not lie solely in the epitaxial recipe; it may also involve the two thin films on the backside of the substrate.

Although a backside seal is not located on the device surface, it affects dopant transport, metallic impurity gettering, film stress, and edge integrity. Understanding it requires more than thinking of it as "a protective layer on the back."

In this article, a backside seal refers to a functional film system deposited on the rear surface of a silicon wafer. A common composite structure, listed from the silicon substrate outward, is:

Single-crystal silicon substrate backside → Poly-Si (polysilicon) → LTO SiO₂ (low-temperature oxide cap)

The two layers perform different functions. Poly-Si provides backside extrinsic gettering and can also help suppress dopant escape to some extent. The outer SiO₂ layer primarily serves as a diffusion barrier and isolates the underlying film. Actual products may instead use LTO alone, Polyback alone, or more complex multilayer combinations. Okmetic, for example, lists LTO backseal, Polyback, and Poly-LTO- Poly supersealing among its options. "Backside seal" is therefore a functional category, not one fixed stack.

It should not be confused with the following three concepts:

• Double-side polishing (DSP): This describes the condition of the front and back surfaces before film deposition. Some backside-seal processes do begin with DSP wafers, but once Poly-Si has been deposited, the backside is covered by a functional film. The finished product should therefore not simply be described as a bare-silicon DSP wafer.
• Epitaxial-grade substrate: This describes the intended use. Backside sealing is one optional form of backside engineering for epitaxial-grade substrates; not every epitaxial substrate requires the same Poly-Si + LTO structure.
• Epitaxial wafer: This is a finished wafer with an epitaxial layer grown on its front surface. A backside-sealed substrate becomes an epitaxial wafer only after epitaxial growth. The backside seal itself is not an epitaxial layer.

In a common process flow, Poly-Si deposition may coat both the front and back surfaces. The polysilicon on the front is subsequently removed by polishing, followed by edge removal and cleaning, leaving the composite film system on the backside. Backside sealing is therefore not an isolated coating step, but a process integrated with polishing, edge removal, and cleaning.

Poly-Si: LPCVD Silane Pyrolysis, with Temperature Determining the Phase

Conventional LPCVD Poly-Si uses the thermal decomposition of silane, which can be simplified as SiH₄

* Si + 2H₂. Kamins' 1980 study of LPCVD silicon films over the range of 525‒725°C is a classic reference in this field: films formed above 600°C are polycrystalline, while those formed at lower temperatures are amorphous, and film texture changes significantly with deposition temperature. Public LPCVD equipment information from National Yang Ming Chiao Tung University provides comparison process points on the same tool: 620°C for Poly-Si and 550°C for amorphous silicon in a silane-based process, as well as 585°C for in situ phosphorus-doped polysilicon.

Thus, common engineering practice places polysilicon deposition above 600°C, often around 620°C. However, the actual temperature must be confirmed against the equipment, film properties, and stress targets. There is no single temperature applicable to every tool.

LTO SiO₂: Low-Temperature Silicon Oxide Deposition Does Not Imply One Tool or One Reaction Path

LTO stands for low-temperature oxide. A silane‒oxygen reaction is a common process route, with a typical industry deposition window of approximately 400‒450°C. "Low temperature" is relative to higher-temperature processes such as thermal oxidation or TEOS-based deposition at approximately 700°C. LTO used for backside sealing may be implemented by APCVD, LPCVD, or other methods. Procurement drawings should specify the required film properties and performance rather than inferring a tool and recipe from the term "LTO" alone.

Thickness: 800/400 Is a Common Structural Example, Not a Universal Standard

Approximately 800 nm of Poly-Si plus approximately 400 nm of SiO₂ is a common example in industry inquiries and drawing discussions, and it can serve as a starting point for technical communication. A publicly available cross-reference is BYU Cleanroom's wafer specification: epitaxial wafers commonly have a characteristic oxide backseal, typically 3000‒5000 Å thick (300‒500 nm), which prevents boron from escaping from the backside during high-temperature epitaxy and contaminating the lightly doped epitaxial layer on the front. This is consistent with the order of magnitude of an approximately 400 nm oxide cap.

It is important to emphasize that the specific Poly-Si and LTO thickness combination varies by supplier, dopant type, and application objective. There is no universal standards basis for presenting 800/400 as an industry-wide specification, or for inferring that production must not exceed a particular thickness

limit.

In other words, particle performance depends on film density + coverage integrity + edge profile + subsequent thermal processing, and cannot be attributed solely to the name of the outermost material.

A thicker Poly-Si film does not simply provide proportionally greater benefits through additional grain boundaries and gettering structures. Intrinsic thin-film stress accumulates as thickness increases, making wafer-warpage control more difficult. Film thickness, deposition temperature, and subsequent thermal history also jointly affect wafer geometric stability. This is why Okmetic lists backside-seal stacks alongside wafer warp/bow optimization as customizable options.

For process integration, at least three categories of results should be evaluated together:

• Incoming geometry: Bow/Warp after film deposition, rather than only bare-wafer data measured before coating;
• Geometry after thermal processing: Warpage and stability after a simulated epitaxial thermal history, avoiding a situation in which incoming wafers pass but post-epitaxy wafers fall out of control;
• Edge and epitaxial defects: Edge-removal width, residual edge films, nodules, particles, epitaxial haze, and related defects.

A backside seal is not "the thicker, the better." It is a trade-off among barrier performance, gettering, stress, and edge behavior.

Backside sealing is particularly worth evaluating in processes that combine a heavily doped substrate with a lightly doped epitaxial layer, include a highly doped buried layer, or are sensitive to epitaxial resistivity uniformity. Application discussions often involve power devices and BCD platforms. Public supplier options are also available: Okmetic's power-device wafer page for 200 mm and 150 mm products explicitly lists Etched, Polyback, and LTO backside treatments.

This should not be oversimplified in reverse to mean that "every BCD process requires 800/400." Whether Poly-Si + LTO is needed should be determined jointly by substrate dopant type and concentration, buried layers, epitaxial thickness and resistivity, thermal budget, and the edge-defect budget.

For procurement and process integration, the following items should be included in drawings and verification plans:

1. Film system: Materials, stack sequence, target thickness of each layer, and tolerances. Do not accept only "BS" or "Superseal" as the specification;
2. Edge condition: Edge-removal method, edge exclusion, coverage at the notch and bevel, and permissible residual edge films;
3. Geometry: Bow/Warp under a defined measurement condition, with agreement on repeat measurement after epitaxy or an equivalent thermal history;
4. Electrical verification: Radial resistivity profiles after epitaxy, such as SRP measurements, with particular attention to near-edge regions and abrupt transitions rather than only the wafer center;
5. Contamination and defect verification: Backside and edge particles, epitaxial nodules, and haze. Where metallic contamination control is required, agree on the corresponding gettering evaluation method.

Supplier terminology also needs interpretation. Okmetic uses "LTO backsealing," "Polyback sealing," and "Poly-LTO-Poly supersealing," while academic literature often uses PBS (Polysilicon Back Seal). Names may differ, but the structure must be unambiguous. When working with other suppliers, the specific backside-seal options should likewise be confirmed against current product drawings, specifications, and mutual qualification results, rather than inferred from a product-line name.

• Okmetic - Discrete Power Device Wafers (LTO backsealing, Polyback, Poly-LTO-Poly supersealing, and 200 mm specifications): https://www.okmetic.com/silicon-wafers/power-wafer-line/discrete- power-device-wafers/
• BYU Cleanroom - Wafer Specifications (typical 3000‒5000 Å oxide backseal on epitaxial wafers; backside polysilicon gettering): https://cleanroom.byu.edu/EW_wafer_specs
• National Yang Ming Chiao Tung University Nano Center - Low Pressure Chemical Vapor Deposition System (LPCVD) (process points including Poly-Si at 620°C and amorphous silicon at 550°C): https://scholar.nycu.edu.tw/en/equipments/low-pressure-chemical-vapor-deposition-system- lpcvd/
• T. I. Kamins, Structure and Properties of LPCVD Silicon Films, J. Electrochem. Soc. 127(3), 686 (1980) (polycrystalline films above 600°C and amorphous films below): https://iopscience.iop.org/article/10.1149/1.2129733
• S. Ogushi et al., Gettering Characteristics of Heavy Metal Impurities in Silicon Wafers with Polysilicon Back Seal and Internal Gettering, Jpn. J. Appl. Phys. 36, 6601 (1997): https://iopscience.iop.org/article/10.1143/JJAP.36.6601

Disclaimer: This article is compiled from publicly available paper abstracts, university equipment information, and supplier webpages for technical communication and sourcing-reference purposes only. The thicknesses, temperatures, and structures discussed are public examples or common industry process windows; they do not constitute standard specifications or guarantees from any supplier. Production qualification should be based on mutually approved drawings, current specifications, defined measurement conditions, and actual epitaxial verification results.